Parity check polytope projection is the most complex part of alternating direction method of multipliers (ADMM) decoding. Due to the complex calculation of check polytope projection, there is no efficient hardware implementation scheme for ADMM decoding algorithm. Using the line segment projection algorithm (LSA) to calculate the check polytope projection can save the complicated sorting and iterative operations, and only need to perform simple addition, subtraction and comparison operations, which is very suitable for hardware implementation. Firstly, the line segment projection algorithm is simplified for hardware implementation and a complete hardware implementation scheme of ADMM decoding is designed. Then, the complete decoding platform is built on FPGA for the experiments. Experiments show that compared with the existing decoder, the frame error rate performance of the ADMM-LSA decoder implemented in this paper is basically the same, the decoding speed is increased by 30.6%. And there is a significant reduction in hardware resource consumption, among which the LUT resource usage can be saved by 40.3%, FF resource can be saved by 67.6%, DSP resource can be saved by 54.5%.