For reduced cost, shorten the design cycle and improved the portability, This paper presented in detail the results of the description of a 32bit single floating-point adder, which was synthesized on CycloneIII chip of Field Programmable Gate Array (FPGA). The adder unit using VHDL language description and pipeline structure, met IEEE754 single precision floating point format and storage format, And the implement and simulation used QuartusII MATLAB and ModelSim SE. Simulation results shows that the system can reach 10-8 precision of magnitude, at the same time the design can be re-configurable and be used as a subsystem in other digital signal processing systems.
参考文献
相似文献
引证文献
引用本文
王秀芳,侯振龙,曲萃萃,等. 基于FPGA的高速浮点加法器的实现[J]. 科学技术与工程, 2010, (25): . WANG Xiu-fang, HOU Zhen-long. Design and Implement of a floating point adder unit using FPGA[J]. Science Technology and Engineering,2010,(25).