Bandwidth and sampling rate of the ADCs used in radar and communication systems are becoming higher and higher. Meanwhile ADC interfaces are being developed from parallel ports to serial JESD204B. In order to meet the performance measurement requirements in the design, manufacturing, sample evaluating and application development procedure of ADC chips, a test platform for high speed ADCs was designed after the ADC specifications and the test methods investigated. The test platform is based on an architecture constructed of high-performance FPGA and DSP, with the data capturing and performance analysis software developed. Experiments were carried out with multiple types of ADCs tested using the proposed platform. These ADCs under test features both in different types of interfaces and in sampling rates ranging from 240 MSPS to 5 GSPS. The results show that the proposed platform is characterized by flexible interface, strong computing ability and high real-time processing, and it can achieve the performance measurement of the newest ADCs.